RISC-V in the context of QEMU

⭐ Core Definition: RISC-V

RISC-V (pronounced "risk-five") is a free and open standard instruction set architecture (ISA) based on reduced instruction set computer (RISC) principles. Unlike proprietary ISAs such as x86 and ARM, RISC-V is described as "free and open" because its specifications are released under permissive open-source licenses and can be implemented without paying royalties.

RISC-V was developed in 2010 at the University of California, Berkeley as the fifth generation of RISC processors created at the university since 1981. In 2015, development and maintenance of the standard was transferred to RISC-V International, a non-profit organization based in Switzerland with more than 4,500 members as of 2025.

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👉 RISC-V in the context of QEMU

The Quick Emulator (QEMU) is a free and open-source emulator that uses dynamic binary translation to emulate a computer's processor; that is, it translates the emulated binary codes to an equivalent binary format which is executed by the machine. It provides a variety of hardware and device models for the virtual machine, enabling it to run different guest operating systems. QEMU can be used with a Kernel-based Virtual Machine (KVM) to emulate hardware at near-native speeds. Additionally, it supports user-level processes, allowing applications compiled for one processor architecture to run on another.

QEMU supports the emulation of x86, ARM, PowerPC, RISC-V, and other architectures.

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⭐ Core Definition: RISC-V
👉 RISC-V in the context of QEMU
RISC-V in the context of CompCert
RISC-V in the context of Load/store architecture

RISC-V in the context of CompCert

CompCert is a formally verified optimizing compiler for a large subset of the C99 programming language (known as Clight) which currently targets PowerPC, ARM, RISC-V, x86 and x86-64 architectures. This project, led by Xavier Leroy, started officially in 2005, funded by the French institutes ANR and INRIA. The compiler is specified, programmed and proven in the Rocq proof assistant. It aims to be used for programming embedded systems requiring reliability. The performance of its generated code is often close to that of GCC (version 3) at optimization level -O1, and always better than that of GCC without optimizations.

Since 2015, AbsInt offers commercial licenses, provides support and maintenance, and contributes to the advancement of the tool. CompCert is released under a noncommercial license, and is therefore not free software, although some of its source files are dual-licensed with the GNU Lesser General Public License version 2.1 or later or are available under the terms of other licenses.

View the full Wikipedia page for CompCert

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RISC-V in the context of Load/store architecture

In computer engineering, a load–store architecture (or a register–register architecture) is an instruction set architecture that divides instructions into two categories: memory access (load and store between memory and registers) and ALU operations (which only occur between registers).

Some RISC architectures such as PowerPC, SPARC, RISC-V, ARM, and MIPS are load–store architectures.

View the full Wikipedia page for Load/store architecture

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⭐ Core Definition: RISC-V

👉 RISC-V in the context of QEMU

RISC-V in the context of CompCert

RISC-V in the context of Load/store architecture