Ones' complement in the context of Full adder

Signed zero is zero with an associated sign. In ordinary arithmetic, the number 0 does not have a sign, so that −0, +0 and 0 are equivalent. However, in computing, some number representations allow for the existence of two zeros, often denoted by −0 (negative zero) and +0 (positive zero), regarded as equal by the numerical comparison operations but with possible different behaviors in particular operations. This occurs in the sign-magnitude and ones' complement signed number representations for integers, and in most floating-point number representations. The number 0 is usually encoded as +0, but can still be represented by +0, −0, or 0.

The IEEE 754 standard for floating-point arithmetic (presently used by most computers and programming languages that support floating-point numbers) requires both +0 and −0. Real arithmetic with signed zeros can be considered a variant of the extended real number line such that ⁠1/−0⁠ = −∞ and ⁠1/+0⁠ = +∞; division is undefined only for ⁠±0/±0⁠ and ⁠±∞/±∞⁠.

Two's complement is the most common method of representing signed (positive, negative, and zero) integers on computers, and more generally, fixed point binary values. As with the ones' complement and sign-magnitude systems, two's complement uses the most significant bit as the sign to indicate positive (0) or negative (1) numbers, and nonnegative numbers are given their unsigned representation (6 is 0110, zero is 0000); however, in two's complement, negative numbers are represented by taking the bit complement of their magnitude and then adding one (−6 is 1010). The number of bits in the representation may be increased by padding all additional high bits of negative or positive numbers with 1's or 0's, respectively, or decreased by removing additional leading 1's or 0's.

Unlike the ones' complement scheme, the two's complement scheme has only one representation for zero, with room for one extra negative number (the range of a 4-bit number is −8 to +7). Furthermore, the same arithmetic implementations can be used on signed as well as unsigned integersand differ only in the integer overflow situations, since the sum of representations of a positive number and its negative is 0 (with the carry bit set).

An adder, or summer, is a digital circuit that performs addition of numbers. In many computers and other kinds of processors, adders are used in the arithmetic logic units (ALUs). They are also used in other parts of the processor, where they are used to calculate addresses, table indices, increment and decrement operators and similar operations.

Although adders can be constructed for many number representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers.In cases where two's complement or ones' complement is being used to represent negative numbers, it is trivial to modify an adder into an adder–subtractor.Other signed number representations require more logic around the basic adder.